1. Field of the Invention
The present invention generally relates to a serial bus controller using a nonvolatile ferroelectric memory, and more specifically, to a memory controller using a nonvolatile ferroelectric register which is configured to adjust variable access time according to addresses when data are exchanged through a serial bus.
2. Description of the Prior Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.
The FRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
The technical contents on the above FRAM are disclosed in the Korean Patent Application No. 2002-85533 by the same inventor of the present invention. Therefore, the basic structure and the operation on the FRAM are not described herein.
In a conventional FRAM, since a column addressing as a page address does not require an extra sensing process during data access, data stored in a sense amplifier page buffer are immediately outputted.
However, during data access, a row addressing further performs an operation of sensing and amplifying data stored in a cell and an operation of maintaining the data in a sense amplifier for a predetermined time. In another row addressing after a row addressing, restore time (precharge time) is added to the row access time. As a result, the row address requires more data access time than the column address. Therefore, in the conventional FRAM, the access time is ineffectively controlled regardless of kinds of address during data access, which results in degradation of reliability of a memory chip.
As a result, an apparatus is required wherein unnecessary data access time may be reduced by controlling interface with a serial bus using the FRAM and program data stored in a memory may be preserved when a power is turned off.